IEEE International Conference on Microelectronic Test Structures

ICMTS 2026 Program

08:30		Registration Desk Opens
09:00		Opening Remarks Y. Fukuzaki (General Chair), K. Xia (Technical Program Chair)¹, T. Ohguro (Technical Program Chair)² Rapidus US, LLC, USA ¹TSMC ²Toshiba Electric Devices & Storage Corporation
Session 1: Circuits for Test and Computation
09:10	1.1	Ultra-low leakage power switch for RO array characterization in 18nm FD-SOI technology platform validation C. Cagli, H. Degoirat, M. Lamy, F. Pourchon, J. B. Moulard, F. Granoux, M. Dahmani, R. Wilson STMicroelectronics, 850 Rue Jean Monnet, Crolles, France
09:30	1.2	Statistical Capacitance Measurement of Si Trench Capacitors Using 3D Stacked Array Test Circuit Ryoya Nishimaki, Koga Saito, Takezo Mawaki, Rihito Kuroda Graduate School of Engineering, Tohoku University
09:50	1.3	Influence of solder bumps-induced mechanical constraint on the performance of BJT ring oscillators M. Dahmani, S. Gallois-Garreignot, M. Dugor, B. Van-Haaren, L. Broussous, F. Belfils, C. Cagli STMicroelectronics, 850 Rue Jean Monnet, Crolles, France
10:10	1.4	Improving Robustness of Leakage-Based MOSFET Reservoir Computing Using Adaptive Pulse-Width Control Ryuto Seki, Masami Utsunomiya, Yu-Guang Chen¹, Hiromitsu Awano, Takashi Sato Graduate School of Informatics, Kyoto University Yoshida-hon-machi, Sakyo, Kyoto, Japan ¹Department of Electrical Engineering, National Central University, Taiwan
10:30		Break
Session 2: AI and Machine Learning
10:50	2.1	Machine Learning-Based Failure Mode Detection in 3D-DRAM Gate-All-Around Select Transistors Jerome Mitard, Husnu Murat Kocak, Romain Ritzenthaler, Nouredine Rassoul, Eren Canga, A. Belmonte Compute Technology Device Department, IMEC, Belgium
11:10	2.2	Speeding Up Capacitance-Voltage Measurements Using Gaussian Processes and Active Learning Husnu Murat Kocak, Hiroaki Arimura¹, Jerome Mitard¹, Jesse Davis Department of Computer Science, KU Leuven, Celestijnenlaan 200A, Leuven, Belgium ¹Compute Technology Device Department, IMEC, Remisebosweg 1, Leuven, Belgium
11:30	2.3	Accelerating Load-Pull Measurements Using Attentive Neural Processes Jui-Yang Hsu, Yu-Ting Chen, Bo-Yuan Chen, Chao-Wen Lin, Chia-Wei Chuang, Chuang-Ju Lin, Kun-Ming Chen, Guo-Wei Huang Taiwan Semiconductor Research Institute, National Institutes of Applied Research
11:50	2.4	VQ-VAE–Based Test Structure Generation for Constructing Design-Fabrication Surrogate Models Ryugo Shimamura, Shun Yasunaga, Tomoya Nakamura, Chen Wang¹, Michael Kraft¹, Yoshio Mita The University of Tokyo, EEIS ¹KU Leuven, ESAT/MNS
12:10		Lunch
Session 3: Device Characterization
13:30	3.1	On-Wafer Golden Devices and Layout Structures for Long-term Prober Chuck Temperature Verification and Monitoring Wuxia Li, Kejun Xia¹, Lei Chao, Shimeng Zhang NXP Semiconductors, Front End Innovation ¹TSMC, Power Management Business Development
13:50	3.2	Monte Carlo simulation method for distance-dependent mismatch and comparison of common-centroid and dispersion layouts Kejun Xia TSMC, Power Management Business Development
14:10	3.3	Optimum Setting of 1/f Noise System towards Ultra-low- noise Floor and Best Practice for Multi-finger MOSFET Noise Characterization Lei Chao, Shimeng Zhang, Jeroen van Beurden, Andries Scholten, Wuxia Li NXP Semiconductors, Front End Innovation
14:30	3.4	Evaluation of Dummy Biasing on Leakage and Noise Performance in 4-nm FinFET Process Seunghyun Noh, Jinho Choi, Yoongeun Seun, SungJoon Park, Jooyoung Song Samsung Electronics, Giheung-gu, Yongin-si, Republic of Korea
14:50		Break
15:10		Exhibitors
Session 4: Process Characterization
15:50	4.1	Defect profiling of Al₂O₃-passivated InGaP layers via planar test structures Paolo La Torraca, Pavel Kirilienko¹, Rajan Bharti, Muskan Jain, Satish Bonam, Lida Ansari, Farzan Gity, Karim Cherkaoui², Alexander Tonkikh², Dmitry Sizov², Paul Gore², Michael Grundmann, Paul K. Hurley Tyndall National Institute, Cork, Ireland ¹Tyndall National Institute, Cork, Ireland Tyndall National Institute, Cork, Ireland ²Meta Reality Labs
16:10	4.2	Extraction of Shockley-Read-Hall lifetime at the InGaP/Al₂O₃ interface using transient capacitance relaxation Pavel Kirilienko, Paolo La Torraca, Rajan Bharti, Muskan Jain, Satish Bonam, Lida Ansari, Farzan Gity, Karim Cherkaoui, Emanuele Pelucchi, Gediminas Juska, Alexander Tonkikh, Andreas Arnlind, Dmitry Sizov, Paul Gore, Michael Grundmann, Paul K. Hurley Tyndall National Institute, Cork, Ireland
16:30	4.3	Accuracy Limits of TLM and CTLM Test Structures for Ultra- Low Contact Resistance Extraction in InGaAs/InP Technologies Anouk Lubben, Yi Wang, Yuqing Jiao, Johan Klootwijk Eindhoven Hendrick Casimir Institute, Eindhoven University of Technology, Eindhoven, the Netherlands
16:50		End of Day 1

Day 2: Wednesday, Mar 25

08:30		Registration Desk Opens
09:00		Invited Talk 1 : Micro Biomolecular Sensors: A Review and Challenges Chih-Ting Lin Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Session 5: MEMS and Sensors
10:00	5.1	A Contact-Closing Test Structure for Electrical In-Chamber Release Endpoint Detection During Vapor HF Etching Akihiko Yoshida, Shun Yasunaga, Ryosho Nakane, Akio Higo, Yoshio Mita The University of Tokyo
10:20	5.2	Comparative Study of Transducer Materials for Sodium- Selective EGISFETs: Stability Improvement and Interference Rejection Kai-Chun Huang, Yan-You Zhou, Chih-Ting Lin Graduate Institute of Electronic Engineering, National Taiwan University
10:40	5.3	An Ultra-Thin Indium Oxide FET Test Structure for Sweat Ion Sensing Jheng-Ru Wu, Yu-Ta Chen¹, Chien-Fu Chen Graduate School of Advanced Technology, National Taiwan University ¹Nano Electromechanical Systems Research Center, National Taiwan University
11:00		Break
Session 6: Memory
11:20	6.1	Read Current in Ferroelectric Tunnel Junctions: Transient versus DC Contributions and Trap Related Effects F. Driussi, M. Segatto, M. Massarotto, L. Carpentieri¹, S. Slesazeck¹, D. Esseni DPIA, Università degli Studi di Udine, Via delle Scienze 206, Udine, Italy ¹NaMLab gGmbH, Nothnitzer Str. 64a, 01187 Dresden, Germany
11:40	6.2	MRAM Wafer Level Adaptative Edge Testing for E icient Yield and Reliability Control Maximilian Liehr, Sean Ogden, Mark Raymond, Kyle Funk, Herve Elemva, Kilho Lee, Gen Feng, Karsten Beckmann, Antoine Chavent¹, Tien Dang Ngoc¹, Daniel Grout¹, Steven Lequeux¹, Siamak SALIMY¹ NY CREATES, 253 Fuller Road, Albany, NY 12203, USA ¹Hprobe Mycronic, 4 rue Joliot Curie, 38320 Eybens, France
12:00	6.3	Comparison of Addressing Methods for Memory Array Characterization Martin Arteaga Castillo, Vincenzo Della Marca¹, Marc Bocquet¹, Jeremy Postel-Pellerin¹, Olivier Paulet, Loic Welter, Matthias Vidal-Dho, Baptiste Chatelier, Brice Arrazat Department of Technology and Design Platforms, STMicroelectronics, Rousset, France ¹Aix-Marseille University, IM2NP, CNRS, UMR 7334, Marseille, France
12:20	6.4	On-Chip Learning with EEPROM Based Synapses: Reliability and Performance Assessment Thibault BERGAMASCHI, Bastien IMBERT, Vincenzo DELLA-MARCA, Sebastien PERRIN, Arnaud REGNIER¹, Madjid AKBAL¹, Christian RIVERO¹, Nicolas ZAMMIT¹, Thibault KEMPF¹, Jorge-Daniel AGUIRRE-MORALES, Jean-Michel PORTAL, Marc BOCQUET Aix-Marseille Univ, Université de Toulon, CNRS, IM2NP, Marseille, France ¹STMicroelectronics Rousset, France
12:40		Lunch
Session 7: Reliability
14:00	7.1	Characterization of Non-conducting RF Hot Carrier Stress Impact on transistor noise from 10 MHz to 26.5 GHz in 5-nm FinFETs G. Niu, X. Ding, H. Zhang¹, W. Wang¹, K. Imura¹ ECE Department, Auburn University, Auburn, AL, USA ¹Maxlinear Inc., Carlsbad, CA, USA
14:20	7.2	Impact of Fluorine Incorporation on Boron Diffusion and Reliability in Advanced High Voltage FinFETs Jia-Hong Lin, Po-Hsun Chen¹, Ling, Tang², Meng-Xuan Feng³, Ting-Chang Chang⁴ Department of Physics, National Sun Yat-sen University, Kaohsiung, 80424, Taiwan ¹Department of Electronic Engineering, I-Shou University, Kaohsiung 840, Taiwan ²Institute of Advanced Semiconductor Packaging and Testing, National Sun Yat-sen University, Kaohsiung, 80424, Taiwan ³Department of Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, 811213, Taiwan ⁴Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan
14:40	7.3	Parasitic Characterization of Hot-Carrier-Induced Degradation using Experimental S-Parameters for RF- MOSFETs Chika Tanaka, Tatsuya Suzuki, Atsushi Sueoka, Fumie Fujii, Kazuya Matsuzawa Memory Division, Kioxia Corporation, Japan
15:00	7.4	Reliability Comparison under Drain Bias Stress for N- and P-Type LTPS Thin-Film Transistors Meng-Xuan Feng, Po-Wen Chang, Sheng-Po Chang, Jia-Hong Lin¹, Tsung-Ming Tsai² Microelectronics Engineering, National Kaohsiung University of Science and Technology, Taiwan ¹Department of Physics, National Sun Yat-sen University, Taiwan ²Department of Materials and Optoelectronic Science, National Sun Yat-Sen University,Taiwan
15:20		Break
15:40		ICMTS 2027 Presentation Francesco Driussi Università degli Studi di Udine
Session 8: ESD
15:50	8.1	Test Structures to Study Interconnection Metal/Via/Contact Reliability under Transient Pulse Stresses of ESD and Surge Events Pi-Yuan Hsiao, Chia-Tsen Dai¹, Tung-Yang Chen¹, Ming-Dou Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan ¹AIP Technology Corporation, Taiwan Branch
16:10	8.2	The Influence of Skin Effect on Metal Lines in ESD Protection Circuit Cheng-Han Chiang, Chun-Yu Lin Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
16:30	8.3	Investigation on ESD Robustness of SiC Devices by Transmission Line Pulse Measurement for Monolithic Integration Applications Hung-Yu Huang, Ya-Zhi Hu¹, Ming-Dou Ker¹ Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University, Hsinchu, Taiwan ¹Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
16:50		End of Day 2
17:30		Banquet

Day 3: Thursday, Mar 26

08:45		Invited Talk 2 : Evaluation, Operando Analysis, and Thermal Modeling of Nanosheet Gas Sensors Ken Uchida The University of Tokyo
Session 9: Cryogenics
09:35	9.1	Impact of Contacts and Heatsinks on Heat Accumulation in Cryogenic SOI MOSFETs Kosuke Hatta, Takayuki Mori, Shota Kondo, Hiroshi Oka¹, Takahiro Mori¹, Jiro Ida Kanazawa Institute of Technology, Ishikawa, Japan ¹National Institute of Advanced Industrial Science and Technology, Ibaraki, Japan
09:55	9.2	Maintaining Constant Vth from 1.7 K to 390 K Using adaptive back gate bias in 22 FDX technology Ergen Tao, Guofu Niu, Anni Zhang, Yili Wang ECE Department, Auburn University, Auburn, AL, USA
10:15	9.3	Characteristics of P-type Polysilicon Resistors from Cryogenic to High Temperatures and Modeling Yili Wang, Kejun Xia¹, Guofu Niu, Jim Xia², Michael Hamilton ECE Department, Auburn University, Auburn, AL, USA ¹TSMC, Hsinchu, Taiwan ²BASIS Chandler, Arizona, USA
10:35		Break
Session 10: Power Devices
10:50	10.1	Investigation of Crystal-Face-Resolved Gate Switching Instability in 4H-SiC UMOSFETs Enabled by a Source-Separated Single-Cell Structure Wei-Jhe Liao, Chia-Lung Hung¹, Yi-Kai Hsiao¹, Bing-Yue Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan ¹Semiconductor Research Center, Hon Hai Research Institute, Hsinchu, Taiwan
11:10	10.2	Evaluation of Rise-Time Effects on AC-TDDB Characteristics in SiC MOSFETs Using an In-Situ Gate Leakage Measurement Technique S. NAKATA, T. SATO Kanazawa Institute of Technology, Japan
11:30	10.3	Application of a three-terminal TCAD model for designing shielded field-limiting ring edge termination Kiyoshi Takeuchi, Munetoshi Fukui, Takuya Saraya, Kazuo Itou, Toshihiko Takakura, Shinichi Suzuki, Hiroyuki Takase, Toshiro Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan
11:50	10.4	Optimizing LDMOS Device Performance and Reliability Through Drift-Region Engineering Po-Wen Chang, Jia-Hong Lin¹, Meng-Xuan Feng, Sheng-Po Chang, Po-Hsun Chen² Department of Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan ¹Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan ²Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan
12:10		Best Paper Award, Closing
12:20		Lunch and Excursion

Session 1: Circuits for Test and Computation

Session 2: AI and Machine Learning

Session 3: Device Characterization

Session 4: Process Characterization

Session 5: MEMS and Sensors

Session 6: Memory

Session 7: Reliability

Session 8: ESD

Session 9: Cryogenics

Session 10: Power Devices